Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models (ENHANCE)
Overview
Since the advent of programmable graphics processing units, accelerators are also more commonly used in HPC to compute jobs cost efficiently on considerably smaller clusters. ENHANCE aims at simplifying the necessary software development for these heterogeneous architectures by automatic parallelization and translation of loops as well as by extending the operating system with a scheduler that enables fair sharing of the accelerators computation time among processes. We will demonstrate and evaluate the development tools and design methods developed in ENHANCE by applying them to practical applications from the domains of bioinformatics, automotive computing, simulation of pollutant spread, and thermodynamics.
Partners & Associated Partners
- Universität Paderborn, Paderborn Center for Parallel Computing (PC²)
- Johannes Gutenberg Universität Mainz
- Konrad-Zuse-Zentrum für Informationstechnik Berlin
- Fraunhofer-Institut für Algorithmen und wissenschaftliches Rechnen (SCAI), St. Augustin
- Universität Bielefeld, Center for Biotechnology (CeBiTec)
- tms technisch-mathematische studiengesellschaft mbh, Bonn
- TWT GmbH Science & Innovation, Neuhausen
- GETLIG & TAR, Falkensee
Duration
04/2011 - 10/2013
References and contact information
Jun.-Prof. Dr. Christian Plessl,
Universität Paderborn, Paderborn Center for Parallel Computing (PC²)
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