Performance and Efficiency in HPC with Custom Computing


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Project duration
July 2017 - July 2020
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Energy Efficiency Performance Analysis


Numerous research projects have demonstrated that accelerators like field-programmable gate arrays (FPGAs), many-cores and graphics processing units (GPUs) can achieve substantial performance and energy-efficiency benefits for high-performance computing. Still, accelerators are not pervasively used so far – even for applications that could very likely profit from accelerators. There are numerous reasons fro the reluctance of HPC developers to adopt accelerators, such as: lack of technical knowledge; unclear benefit of the time invested for porting and optimization; lack of an estimate of the acceleration potential; poor quality of materials that teach the use of accelerators; few libraries that allow a black-box use of accelerators.

In this project, we are establishing a structured support and consulting process in our HPC center that supports HPC developers during the complete process from performance analysis and estimation of the acceleration potential up to the optimization of the runtime-critical parts of their applications. This process infuses a complementary expertise into teams of developers from computational sciences and thus improves the cost/benefit ratio of code porting and optimization. Thus ultimately allows these scientists to reduce the program runtime or to simulate larger or more complex systems.

To allow developers to profit from previous work we will translate frequently used functions into reusable libraries. Finally, we will develop teaching materials that are tailored to the needs of computational scientists and collect code examples that illustrate best practices.

We will focus the work in this project on the technological and application-related or method-related competencies of our compute center and its users. As research of our main users work is concentrated in three main domains (nanophotonics, molecular dynamics and quantum chemistry) we can reuse domain-specific methods and experiences for different codes. Technologically, we will focus on FPGAs as accelerator technology, because FPGAs have the highest potential to improve the energy efficiency of computation and the market for FPGAs is currently thriving. We see a fertile basis for our research and development efforts, driven by first initiatives to standardize software stacks for FPGAs, the beginning of hardware integration of FPGA technologies in processors, the introduction of CAPI as a general accelerator interface by IBM and the increased maturity of FPGA development tools. We expect that our substantial expertise in custom computing with FPGAs and our focus on few application domains provide ideal conditions to make a significant progress in the application of FPGAs in HPC and allow for demonstrating and quantifying the potential to improve the performance and energy efficiency with real HPC codes.


Project partners


Prof. Dr. Christian Plessl

Administrative contact

Prof. Dr. Christian Plessl
Universität Paderborn
Paderborn Center for Parallel Computing
Warburger Str. 100
33098 Paderborn